1. Field of the Invention
This invention relates to analog interface circuits and more particularly to an analog interface system that has an Analog to Digital (A-to-D) converter for transmitting digital information to digital signal processors and a Digital to Analog (D-to-A) converter for receiving digital information from the digital signal processor (DSP) and converting to analog for outputting, where the analog interface circuit advances or retards the conversion timing by an amount determined by the digital signal processor.
2. Description of the Prior Art
In the past, when an analog interface circuit requires changing of the conversion rates of either the A-to-D converter or the D-to-A converter, the digital signal processor with which the analog interface circuit is associated determines how much the conversion time should be advanced or retarded, and actually implements such a change by generating a correcting pulse that is sent to the analog interface circuit timing. Generally, the extent of such an advance or retardation is plus or minus one master clock cycle.
U.S. Pat. No. 4,638,451--"Microprocessor System with Programmable Interface" issued on Jan. 20, 1987 and assigned to the assignee of this invention involves a microprocessor system that includes an analog input channel and an analog output channel. The analog input channel has an A-to-D converter and the analog output channel has a D-to-A converter. These converters have conversion sampling rates that may be retarded or advanced by one master clock cycle as determined by the associated digital signal processor. After such change, the system goes back to its original conversion rate.
According to the present invention, the digital signal processor simply determines the number of clock cycles (1 to 32 in this preferred embodiment) to be added or subtracted to the conversion timing and transmits that number, upon request to the analog interface circuit. The analog interface circuit then adds or subtracts the number of master clock cycles to the conversion timing to actually implement the change in timing.
By relieving the digital signal processor of its duty to implement such an increment/decrement operation, the present invention enables the digital signal processor to perform other tasks.